View M48T201Y-70MH1_1609898.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/32 may 2002 m48t201y m48t201v 5.0 or 3.3v timekeeper ? supervisor features summary n converts low power sram into nvrams n year 2000 compliant n battery low flag n integrated real time clock, power- fail control circuit, battery and crystal n watchdog timer n choice of write protect voltages (v pfd = power-fail deselect voltage): m48t201y: v cc = 4.5 to 5.5v 4.1v v pfd 4.5v m48t201v: v cc = 3.0 to 3.6v 2.7v v pfd 3.0v n microprocessor power-on reset (valid even during battery back-up mode) n programmable alarm output active in the battery backed-up mode n packaging includes a 44-lead soic and snaphat ? top (to be ordered separately) n soic package provides direct connection for a snaphat ? top which contains the battery and crystal figure 1. 44-pin soic package soh44 (mh) snaphat (sh) crystal/battery 44 1
m48t201y, m48t201v 2/32 table of contents description . . ..................................................................4 logic diagram (figure 2.) . ........................................................4 signal names (table 1.) . . . . . . . . . . . . . . . . . . . . . .....................................4 soic connections (figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 hardware hookup (figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .....6 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................7 absolute maximum ratings (table 2.) . . . .... ............................. ...........7 dc and ac parameters. . . . . . . . . . ........... .....................................8 dc and ac measurement conditions (table 3.) . . . .....................................8 ac testing load circuit (figure 5.) . . . . . . . . . .........................................8 capacitance (table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 dc characteristics (table 5.) . . . . . . ........... .....................................9 operation .... .................................................................10 address decoding . . ........... .................................................10 operating modes (table 6.). . . . . . . . ...............................................10 read mode ...................................................................11 g con timing when switching between rtc and external sram (figure 6.) . . . . . . . . . . . . . . . . 11 read cycle timing: rtc and external ram control signals (figure 7.) . . . . ...............12 read mode ac characteristics (table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...13 write mode. . . . . . . . . . . . . . . . . . . . . . . . . . ........................................14 write cycle timing: rtc & external ram control signals (figure 8.) . . . . . . . . . . ..........14 write mode ac characteristics (table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 data retention mode. . . . . .......................................................16 power down/up mode ac waveforms (figure 9.) .....................................16 power down/up mode ac characteristics (table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3/32 m48t201y, m48t201v clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............17 timekeeper ? registers. . . .................................................. ...17 reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ......................... ...17 setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . ....................................17 stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............17 timekeeper ? register map (table 10.) . . . ........................................18 setting the alarm clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........19 alarm interrupt reset waveforms (figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . ...............19 alarm repeat modes (table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 back-up mode alarm waveforms (figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....20 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . ........................................20 square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 square wave output frequency (table 12.). . ........................................21 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...............22 reset inputs (rstin1 & rstin2) . . . . . . . . . . . ............................. ..........22 rstin1 and rstin2 timing waveforms (figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 reset ac characteristics (table 13.) . . . . . . . . . . . . . . . . . ..............................22 calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 initial power-on defaults . . . . . . . . . . .......... .....................................24 default values (table 14.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 crystal accuracy across temperature (figure 13.) ....................................25 calibration waveform (figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 v cc noise and negative going transients. . . . . . . . . . . . . . . ......................... ...26 supply voltage protection (figure 15.) . . . . . . . ............................. ..........26 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........27 snaphat ? battery table (table 16.) ..............................................27 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 revision history. ..............................................................31
m48t201y, m48t201v 4/32 description the m48t201y/v are self-contained devices that include a real time clock (rtc), programmable alarms, a watchdog timer, and a square wave out- put which provides control of up to 512k x 8 of ex- ternal low-power static ram. access to all rtc functions and the external ram is the same as conventional bytewide sram. the 16 time- keeper ? registers offer year, month, date, day, hour, minute, second, calibration, alarm, century, watchdog, and square wave output data. external- ly attached static rams are controlled by the m48t201y/v via the g con and e con signals. the 44-pin, 330mil soic provides sockets with gold plated contacts at both ends for direct con- nection to a separate snaphat ? housing con- taining the battery and crystal. the unique design allows the snaphat battery package to be mounted on top of the soic package after the completion of the surface mount process. insertion of the snaphat housing after reflow prevents potential battery damage due to the high temperatures required for device surface-mount- ing. the snaphat housing is keyed to prevent reverse insertion. the soic and battery packages are shipped separately in plastic anti-static tubes or in tape & reel form. for the 44-lead soic, the battery/crystal package (e.g., snaphat) part number is am4txx-br12sho (see table 16, page 27). caution: do not place the snaphat battery/crys- tal top in conductive foam as this will drain the lith- ium button-cell battery. figure 2. logic diagram table 1. signal names ai02240 19 a0-a18 wdi dq0-dq7 v cc m48t201y m48t201v g v ss 8 e e con g con w rstin2 rstin1 rst irq/ft v out sqw a0-a18 address inputs dq0-dq7 data inputs / outputs rstin1 reset 1 input rstin2 reset 2 input rst reset output (open drain) wdi watchdog input e chip enable input g output enable input w write enable input e con ram chip enable output g con ram enable output irq/ft interrupt / frequency test output (open drain) sqw square wave output v out supply voltage output v cc supply voltage v ss ground nc not connected internally
5/32 m48t201y, m48t201v figure 3. soic connections a1 a0 nc a4 rst wdi a2 a3 a9 a10 a11 g dq7 a17 irq/ft nc e dq6 dq1 dq3 v ss dq4 a13 v out a12 a5 a14 v cc a6 ai02241 m48t201y m48t201v 8 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 20 19 18 17 g con dq0 a18 a16 sqw nc 44 39 38 37 36 35 34 33 a15 a8 dq2 21 dq5 40 43 1 42 41 a7 w rstin2 rstin1 e con
m48t201y, m48t201v 6/32 figure 4. hardware hookup note: 1. if the second chip enable pin (e2) is unused, it should be tied to v out . ai00604 32,768 hz crystal lithium cell a0-a18 dq0-dq7 e v cc w g wdi rstin1 rstin2 v ss e e2 (1) w g v cc v ss a0-axx dq0-dq7 0.1 m f 0.1 m f 5v econ gcon rst irq/ft sqw m48t201y/v cmos sram v out
7/32 m48t201y, m48t201v maximum rating stressing the device above the rating listed in the aabsolute maximum ratingso table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 2. absolute maximum ratings note: 1. reflow at peak temperature of 215 cto225 c for < 60 seconds (total thermal budget not to exceed 180 c for between 90 to 120 seconds). cauti on: negative undershoots below 0.3v are not allowed on any pin while in the battery back-up mode. cauti on: do not wave solder soic to avoid damaging snaphat sockets. symbol parameter value unit t a ambient operating temperature grade 1 0 to 70 c grade 6 40 to 85 c t stg storage temperature snaphat ? 40 to 85 c soic 55 to 125 c t sld (1) lead solder temperature for 10 seconds 260 c v io input or output voltage 0.3 to v cc +0.3 v v cc supply voltage m48t201y 0.3 to 7.0 v m48t201v 0.3 to 4.6 v i o (2) output current 20 ma p d power dissipation 1 w
m48t201y, m48t201v 8/32 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. dc and ac measurement conditions note: output high z is defined as the point where data is no longer driven. figure 5. ac testing load circuit notes:excluding open-drain output pin; 50pf for m48t201v. table 4. capacitance note: 1. effective capacitance measured with power supply at 5v; sampled only, not 100% tested. 2. at 25 c; f = 1mhz. 3. outputs deselected. parameter m48t201y m48t201v unit v cc supply voltage 4.5 to 5.5 3.0 to 3.6 v ambient operating temperature grade 1 0 to 70 0 to 70 c grade 6 40 to 85 40 to 85 c load capacitance (c l ) 100 50 pf input rise and fall times 5 5ns input pulse voltages 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 v ai04764 c l = 100pf c l includes jig capacitance 645 w device under test 1.75v symbol parameter (1,2) min max unit c in input capacitance 10 pf c out (3) input/output capacitance 10 pf
9/32 m48t201y, m48t201v table 5. dc characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70 c or 40 to 85 c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. outputs deselected. 3. rstin1 and rstin2 internally pulled-up to v cc through 100k w resistor. wdi internally pulled-down to v ss through 100k w resistor. 4. for irq/ft & rst pins (open drain). 5. conditioned outputs (e con -g con ) can only sustain cmos leakage currents in the battery back-up mode. higher leakage currents will reduce battery life. 6. external sram must match timekeepe r supervisor chip v cc specification. 7. i bat (osc on) = industrial temperature range - grade 6 device. sym parameter test condition (1) m48t201y m48t201v unit 70 85 min typ max min typ max i li input leakage current 0v v in v cc 1 1 m a i lo (2) output leakage current 0v v out v cc 1 1 m a i cc supply current outputs open 8 15 4 10 ma i cc1 supply current (standby) ttl e=v ih 53ma i cc2 supply current (standby) cmos e=v cc 0.2 32ma i bat battery current osc on 575 800 575 800 na battery current osc on (7) 975 1125 975 1125 na battery current osc off 100 100 na v il input low voltage 0.3 0.8 0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 2.0 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 0.4 v output low voltage (open drain) (4) i ol = 10ma 0.4 0.4 v v oh output high voltage i oh = 1.0ma 2.4 2.4 v v ohb (5) v oh battery back-up i out2 = 1.0 m a 2.0 3.6 2.0 3.6 v i out1 (6) v out current (active) v out1 >v cc 0.3 100 70 ma i out2 v out current (battery back-up) v out2 >v bat 0.3 100 100 m a v pfd power-fail deselect voltage 4.1 4.35 4.5 2.7 2.9 3.0 v v so battery back-up switchover voltage 3.0 v pfd 100mv v v bat battery voltage 3.0 3.0 v
m48t201y, m48t201v 10/32 operation automatic backup and write protection for an ex- ternal sram is provided through v out ,e con , and g con pins. (users are urged to insure that voltage specifications, for both the supervisor chip and external sram chosen, are similar.) the snaphat ? containing the lithium energy source is used to retain the rtc and ram data in the ab- sence of v cc power through the v out pin. the chip enable output to ram (e con ) and the output enable output to ram (g con ) are controlled dur- ing power transients to prevent data corruption. the date is automatically adjusted for months with less than 31 days and corrects for leap years (valid until 2100). the internal watchdog timer provides programmable alarm windows. the nine clock bytes (7ffffh-7fff9h and 7fff1h) are not the actual clock counters, they are memory locations consisting of biport ? read/write memory cells within the static ram array. clock circuitry updates the clock bytes with current information once per second. the informa- tion can be accessed by the user in the same man- ner as any other location in the static memory array. byte 7fff8h is the clock control register. this byte controls user access to the clock infor- mation and also stores the clock calibration set- ting. byte 7fff7h contains the watchdog timer setting. the watchdog timer can generate either a reset or an interrupt, depending on the state of the watch- dog steering bit (wds). bytes 7fff6h-7fff2h include bits that, when programmed, provide for clock alarm functionality. alarms are activated when the register content matches the month, date, hours, minutes, and seconds of the clock registers. byte 7fff1h contains century informa- tion. byte 7fff0h contains additional flag informa- tion pertaining to the watchdog timer, the alarm condition, the battery status and square wave out- put operation. 4 bits are included within this regis- ter (rs0-rs3) that are used to program the square wave output frequency (see table 12, page 21). the m48t201y/v also has its own pow- er-fail detect circuit. this control circuitry con- stantly monitors the supply voltage for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the timekeeper ? regis- ter data and external sram, providing data secu- rity in the midst of unpredictable system operation. as v cc falls below the battery back-up switchover voltage (v so ), the control circuitry automatically switches to the battery, maintaining data and clock operation until valid power is restored. address decoding the m48t201y/v accommodates 19 address lines (a0-a18) which allow direct connection of up to 512k bytes of static ram. regardless of sram density used, timekeeping, watchdog, alarm, cen- tury, flag, and control registers are located in the upper ram locations. all timekeeper registers reside in the upper ram locations without conflict by inhibiting the g con (output enable ram) signal during clock access. the ram's physical locations are transparent to the user and the memory map looks continuous from the first clock address to the upper most attached ram addresses. table 6. operating modes note: x = v ih or v il ;v so = battery back-up switchover voltage 1. see table 9, page 17 for details. mode v cc e g w dq7-dq0 power deselect 4.5v to 5.5v or 3.0v to 3.6v v ih x x high-z standby write v il x v il d in active read v il v il v ih d out active read v il v ih v ih high-z active deselect v so to v pfd (min) (1) x x x high-z cmos standby deselect v so (1) x x x high-z battery back-up
11/32 m48t201y, m48t201v read mode the m48t201y/v executes a read cycle when- ever w (write enable) is high and e (chip en- able) is low. the unique address specified by the address inputs (a0-a18) defines which one of the on-chip timekeeper ? registers or external sram locations is to be accessed. when the ad- dress presented to the m48t201y/v is in the range of 7ffffh-7fff0h, one of the on-board timekeeper registers is accessed and valid data will be available to the eight data output driv- ers within t avqv after the address input signal is stable, providing that the e and g access times are also satisfied. if they are not, then data access must be measured from the latter occurring signal (e or g) and the limiting parameter is either t elqv for e or t glqv for g rather than the address access time. when one of the on-chip timekeeper reg- isters is selected for read, the g con signal will remain inactive throughout the read cycle. when the address value presented to the m48t201y/v is outside the range of timekeep- er registers, an external sram location will be selected. in this case the g signal will be passed to the g con pin, with the specified delay times of t aoel or t oerl . figure 6. g con timing when switching between rtc and external sram ai02333 g e g con taoel address 00000h - 7ffefh 7fff0h - 7ffffh 00000h - 7ffefh 7fff0h - 7ffffh taoeh toerl tro external sram rtc external sram rtc
m48t201y, m48t201v 12/32 figure 7. read cycle timing: rtc and external ram control signals ai02334 g con w dq0-dq7 g e con data out valid address tavav e telqv tavav tavav read read write data in valid data out valid tavqv twhax tavwl telqx tglqv tepd tro tghqz twlwh taxqx tglqx
13/32 m48t201y, m48t201v table 7. read mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70 c or 40 to 85 c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. c l = 5pf. symbol parameter (1) m48t201y m48t201v unit 70 85 min max min max t avav read cycle time 70 85 ns t avqv address valid to output valid 70 85 ns t elqv chip enable low to output valid 70 85 ns t glqv output enable low to output valid 25 35 ns t elqx (2) chip enable low to output transition 5 5 ns t glqx (2) output enable low to output transition 0 0 ns t ehqz (2) chip enable high to output hi-z 20 25 ns t ghqz (2) output enable high to output hi-z 20 25 ns t axqx address transition to output transition 5 5 ns t aoel external sram address to g con low 20 30 ns t aoeh supervisor sram address to g con high 20 30 ns t epd etoe con low or high 10 15 ns t oerl g low to g con low 15 20 ns t ro g high to g con high 10 15 ns
m48t201y, m48t201v 14/32 write mode the m48t201y/v is in the write mode whenever w (write enable) and e (chip enable) are low state after the address inputs are stable. the start of a write is referenced from the latter occurring falling edge of w or e. a write is terminated by the earlier rising edge of w or e. the addresses must be held valid throughout the cycle. e or w must return high for a minimum of t ehax from chip enable or t whax from write enable prior to the initiation of another read or write cycle. data- in must be valid t dvwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus con- tention; although, if the output bus has been acti- vated by a low on e and g a low on w will disable the outputs t wlqz after w falls. when the address value presented to the m48t201y/v during the write is in the range of 7ffffh-7fff0h, one of the on-board time- keeper ? registers will be selected and data will be written into the device. when the address value presented to m48t201y/v is outside the range of timekeeper registers, an external sram loca- tion is selected. figure 8. write cycle timing: rtc & external ram control signals ai02336 g con w dq0-dq7 g e con data in valid address tavav e taveh tavav tavav write write read data out valid data out valid tavwh tavqv twlwh twhdx twhax twhqx tepd tepd tro twlqz tdvwh tglqv tehqz tdveh data in valid teleh tehax tavel tehdx tavwl
15/32 m48t201y, m48t201v table 8. write mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70 c or 40 to 85 c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. c l = 5pf 3. if e goes low simultaneously with w going low, the outputs remain in the high impedance state. symbol parameter (1) m48t201y m48t201v unit 70 85 min max min max t avav write cycle time 70 85 ns t avwl address valid to write enable low 0 0 ns t avel address valid to chip enable low 0 0 ns t wlwh write enable pulse width 45 55 ns t eleh chip enable low to chip enable high 50 60 ns t whax write enable high to address transition 0 0 ns t ehax chip enable high to address transition 0 0 ns t dvwh input valid to write enable high 25 30 ns t dveh input valid to chip enable high 25 30 ns t whdx write enable high to input transition 0 0 ns t ehdx chip enable high to input transition 0 0 ns t wlqz (2,3) write enable low to output high-z 20 25 ns t avwh address valid to write enable high 55 65 ns t aveh address valid to chip enable high 55 65 ns t whqx (2,3) write enable high to output transition 5 5 ns
m48t201y, m48t201v 16/32 data retention mode with valid v cc applied, the m48t201y/v can be accessed as described above with read or write cycles. should the supply voltage decay, the m48t201y/v will automatically deselect, write protecting itself (and any external sram) when v cc falls between v pfd (max) and v pfd (min). this is accomplished by internally inhibiting ac- cess to the clock registers via the e signal. at this time, the reset pin (rst) is driven active and will remain active until v cc returns to nominal levels. external ram access is inhibited in a similar man- ner by forcing e con to a high level. this level is within 0.2v of the v bat .e con will remain at this level as long as v cc remains at an out-of-toler- ance condition. when v cc falls below the level of the battery (v bat ), power input is switched from the v cc pin to the snaphat ? battery and the clock registers are maintained from the attached battery supply. external ram is also powered by the snaphat battery. all outputs except g con , e con , rst, irq/ft and v out , become high im- pedance. the v out pin is capable of supplying 100 m a of current to the attached memory with less than 0.3v drop under this condition. on power up, when v cc returns to a nominal value, write protec- tion continues for 200ms (max) by inhibiting e con . the rst signal also remains active during this time (see figure 9). note: most low power srams on the market to- day can be used with the m48t201y/v time- keeper ? supervisor. there are, however some criteria which should be used in making the final choice of an sram to use. the sram must be designed in a way where the chip enable input disables all other inputs to the sram. this allows inputs to the m48t201y/v and srams to be adon't careo once v cc falls below v pfd (min). the sram should also guarantee data retention down to v cc = 2.0v. the chip en- able access time must be sufficient to meet the system needs with the chip enable (and output en- able) output propagation delays included. figure 9. power down/up mode ac waveforms ai03519 v cc inputs rst outputs don't care high-z tf tfb tr trec trb valid valid v pfd (max) v pfd (min) v so valid valid
17/32 m48t201y, m48t201v table 9. power down/up mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70 c or 40 to 85 c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200 m s after v cc pass- es v pfd (min). 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. 4. t rec (min) = 20ms for industrial temperature grade 6 device. clock operation timekeeper ? registers the m48t201y/v offers 16 internal registers which contain timekeeper ? , alarm, watchdog, flag, and control data (see table 10, page 18). these registers are memory locations which con- tain external (user accessible) and internal copies of the data (usually referred to as biport ? timekeeper cells). the external copies are in- dependent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. time- keeper and alarm registers store data in bcd. control, watchdog and flags (bits d0 to d3) reg- isters store data in binary format. reading the clock updates to the timekeeper registers should be halted before clock data is read to prevent reading data in transition. the biport timekeeper cells in the ram array are only data registers and not the actual clock counters, so updating the reg- isters can be halted without disturbing the clock it- self. updating is halted when a '1' is written to the read bit, d6 in the control register (7fff8h). as long as a '1' remains in that position, updating is halted. after a halt is issued, the registers reflect the count; that is, the day, date, and time that were current at the moment the halt command was is- sued. all of the timekeeper registers are updated si- multaneously. a halt will not interrupt an update in progress. updating occurs approximately 1 sec- ond after the read bit is reset to a '0.' setting the clock bit d7 of the control register (7fff8h) is the write bit. setting the write bit to a '1,' like the read bit, halts updates to the timekeeper reg- isters. the user can then load them with the cor- rect day, date, and time data in 24-hour bcd format (see table 10, page 18). resetting the write bit to a '0' then transfers the values of all time registers (7ffffh-7fff9h, 7fff1h) to the actual timekeeper counters and allows normal operation to resume. after the write bit is reset, the next clock update will occur approximately one second later. note: upon power-up following a power failure, both the write bit and the read bit will be reset to '0.' stopping and starting the oscillator the oscillator may be stopped at any time. if the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. the stop bit is located at bit d7 within the seconds register (7fff9h). setting it to a '1' stops the oscillator. when reset to a '0,' the m48t201y/v oscillator starts within one second. note: it is not necessary to set the write bit when setting or resetting the frequency test bit (ft) or the stop bit (st). symbol parameter (1) min max unit t f (2) v pfd (max) to v pfd (min) v cc fall time 300 m s t fb (3) v pfd (min) to v ss v cc fall time m48t201y 10 m s m48t201v 150 m s t r v pfd (min) to v pfd (max) v cc rise time 10 m s t rec (4) v pfd (max) to rst high 40 200 ms t rb v ss to v pfd (min) v cc rise time 5 m s
m48t201y, m48t201v 18/32 table 10. timekeeper ? register map keys: s = sign bit ft = frequency test bit r = read bit w = write bit st = stop bit 0 = must be set to '0' wds = watchdog steering bit af = alarm flag bl = battery low flag sqwe = square wave enable bit bmb0-bmb4 = watchdog multiplier bits rb0-rb1 = watchdog resolution bits afe = alarm flag enable flag abe = alarm in battery back-up mode enable bit rpt1-rpt5 = alarm repeat mode bits wdf = watchdog flag rs0-rs3 = sqw frequency address data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 7ffffh 10 years year year 00-99 7fffeh 0 0 0 10 m month month 01-12 7fffdh 0 0 10 date date: day of month date 01-31 7fffch 0 ft 0 0 0 day day 01-07 7fffbh 0 0 10 hours hours (24 hour format) hours 00-23 7fffah 0 10 minutes minutes minutes 00-59 7fff9h st 10 seconds seconds seconds 00-59 7fff8h w r s calibration control 7fff7h wds bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 7fff6h afe sqwe abe al.10m alarm month al. month 01-12 7fff5h rpt4 rpt5 al. 10 date alarm date al. date 01-31 7fff4h rpt3 0 al. 10 hours alarm hours al. hours 00-23 7fff3h rpt2 alarm 10 minutes alarm minutes al. minutes 00-59 7fff2h rpt1 alarm 10 seconds alarm seconds al. seconds 00-59 7fff1h 1000 years 100 years century 00-99 7fff0h wdf af 0 bl rs3 rs2 rs1 rs0 flags
19/32 m48t201y, m48t201v setting the alarm clock registers 7fff6h-7fff2h contain the alarm set- tings. the alarm can be configured to go off at a prescribed time on a specific month, day of month, hour, minute, or second or repeat every month, day of month, hour, minute, or second. it can also be programmed to go off while the m48t201y/v is in the battery back-up to serve as a system wake-up call. bits rpt5-rpt1 put the alarm in the repeat mode of operation. table 11 shows the possible config- urations. codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. note: user must transition address (or toggle chip enable) to see flag bit change. when the clock information matches the alarm clock settings based on the match criteria defined by rpt5-rpt1, the af (alarm flag) is set. if afe (alarm flag enable) is also set, the alarm condi- tion activates the irq/ft pin. to disable alarm, write '0' to the alarm-date register and rpt1-5. the irq/ft output is cleared by a read to the flags register as shown in figure 10. a subse- quent read of the flags register is necessary to see that the value of the alarm flag has been re- set to '0.' the irq/ft pin can also be activated in the bat- tery back-up mode. the irq/ft will go low if an alarm occurs and both abe (alarm in battery back-up mode enable) and afe are set. the abe and afe bits are reset during power-up, therefore an alarm generated during power-up will only set af. the user can read the flag register at system boot-up to determine if an alarm was generated while the m48t201y/v was in the deselect mode during power-up. figure 11, page 20 illustrates the back-up mode alarm timing. figure 10. alarm interrupt reset waveforms table 11. alarm repeat modes rpt5 rpt4 rpt3 rpt2 rpt1 alarm setting 1 1 1 1 1 once per second 1 1 1 1 0 once per minute 1 1 1 0 0 once per hour 1 1 0 0 0 once per day 1 0 0 0 0 once per month 0 0 0 0 0 once per year ai02331 a0-a18 active flag bit address 7fff0h irq/ft 15ns min high-z
m48t201y, m48t201v 20/32 figure 11. back-up mode alarm waveforms watchdog timer the watchdog timer can be used to detect an out- of-control microprocessor. the user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 7fff7h. bits bmb4-bmb0 store a binary multiplier and the two lower order bits rb1-rb0 select the resolution, where 00 = 1/16 second, 01 = 1/4 sec- ond, 10 = 1 second, and 11 = 4 seconds. the amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (for example: writing 00001110 in the watchdog register = 3*1 or 3 seconds). note: accuracy of timer is within the selected resolution. if the processor does not reset the timer within the specified period, the m48t201y/v sets the wdf (watchdog flag) and generates a watchdog inter- rupt or a microprocessor reset. wdf is reset by reading the flag register (address 7fff0h). the most significant bit of the watchdog register is the watchdog steering bit (wds). when set to a '0', the watchdog will activate the irq/ft pin when timed-out. when wds is set to a '1,' the watchdog will output a negative pulse on the rst pin for t rec . the watchdog register and the afe, sqwe, abe, and ft bits will reset to a '0' at the end of a watchdog time-out when the wds bit is set to a '1.' the watchdog timer can be reset by two methods: 1. a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (wdi) or 2. the microprocessor can perform a write of the watchdog register. the time-out period then starts over. the wdi pin should be tied to v ss if not used. the watchdog will be reset on each transition (edge) seen by the wdi pin. in order to perform a software reset of the watch- dog timer, the original time-out period can be writ- ten into the watchdog register, effectively restarting the count-down cycle. should the watchdog timer time-out, and the wds bit is programmed to output an interrupt, a value of 00h needs to be written to the watchdog register in order to clear the irq/ft pin. this will also dis- able the watchdog function until it is again pro- grammed correctly. a read of the flags register will reset the watchdog flag (bit d7; register 7fff0h). the watchdog function is automatically disabled upon power-down and the watchdog register is cleared. if the watchdog function is set to output to the irq/ft pin and the frequency test function is activated, the watchdog or alarm function prevails and the frequency test function is denied. note: the user must transition the address (or toggle chip enable) to see the flag bit change. ai03520 v cc irq/ft high-z v pfd (max) v pfd (min) afe bit/abe bit af bit in flags register high-z v so trec
21/32 m48t201y, m48t201v square wave output the m48t201y/v offers the user a programmable square wave function which is output on the sqw pin. rs3-rs0 bits located in 7fff0h establish the square wave output frequency. these frequencies are listed in table 12. once the selection of the sqw frequency has been completed, the sqw pin can be turned on and off under software con- trol with the square wave enable bit (sqwe) lo- cated in register 7fff6h. table 12. square wave output frequency square wave bits square wave rs3 rs2 rs1 rs0 frequency units 0000 hi-z - 0001 32.768 khz 0010 8.192 khz 0011 4.096 khz 0100 2.048 khz 0101 1.024 khz 0110512hz 0111256hz 1000128hz 100164hz 101032hz 101116hz 11008hz 11014hz 11102hz 11111hz
m48t201y, m48t201v 22/32 power-on reset the m48t201y/v continuously monitors v cc . when v cc falls to the power fail detect trip point, the rst pulls low (open drain) and remains low on power-up for t rec after v cc passes v pfd (max). the rst pin is an open drain output and an appro- priate pull-up resistor to v cc should be chosen to control rise time. reset inputs (rstin1 & rstin2) the m48t201y/v provides two independent in- puts which can generate an output reset. the du- ration and function of these resets is identical to a reset generated by a power cycle. figure 12 and table 13 illustrate the ac reset characteristics of this function. pulses shorter than t r1 and t r2 will not generate a reset condition. rstin1 and rstin2 are each internally pulled up to v cc through a 100k w resistor. figure 12. rstin1 and rstin2 timing waveforms table 13. reset ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70 c or 40 to 85 c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. c l = 5pf (see figure 5). 3. t r1hrz or t r2hrz = 20ms for industrial temperature grade 6 device. symbol parameter (1) min max unit t r1 rstin1 low to rst low 50 200 ns t r2 rstin2 low to rst low 20 100 ms t r1hrz (2,3) rstin1 high to rst hi-z 40 200 ms t r2hrz (2,3) rstin2 high to rst hi-z 40 200 ms ai01679 rstin1 rst rstin2 tr1 tr1hrz hi-z tr2 tr2hrz hi-z
23/32 m48t201y, m48t201v calibrating the clock the m48t201y/v is driven by a quartz controlled oscillator with a nominal frequency of 32,768hz. the devices are factory calibrated at 25 c and tested for accuracy. clock accuracy will not ex- ceed 35 ppm (parts per million) oscillator fre- quency error at 25 c, which equates to about 1.53 minutes per month. when the calibration circuit is properly employed, accuracy improves to better than +1/2 ppm at 25 c. the oscillation rate of crystals changes with tem- perature (see figure 13, page 25). the m48t201y/v design employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the di- vide by 256 stage, as shown in figure 14, page 25. the number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value load- ed into the five calibration bits found in the control register. adding counts speeds the clock up, sub- tracting counts slows the clock down. the calibration bits occupy the five lower order bits (d4-d0) in the control register 7fff8h. these bits can be set to represent any value be- tween 0 and 31 in binary form. bit d5 is a sign bit; '1' indicates positive calibration, '0' indicates nega- tive calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or 2.034 ppm of adjustment per calibra- tion step in the calibration register. assuming that the oscillator is running at exactly 32,768hz, each of the 31 increments in the calibration byte would represent +10.7 or 5.35 seconds per month which corresponds to a total range of +5.5 or 2.75 minutes per month. two methods are available for ascertaining how much calibration a given m48t201y/v may re- quire. the first involves setting the clock, letting it run for a month and comparing it to a known accu- rate reference and recording deviation over a fixed period of time. calibration values, including the number of seconds lost or gained in a given peri- od, can be found in the stmicroelectronics appli- cation note an934, atimekeeper ? calibration.o this allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. the designer could provide a simple utility that ac- cesses the calibration byte. the second approach is better suited to a manu- facturing environment, and involves the use of the irq/ft pin. the pin will toggle at 512hz, when the stop bit (st, d7 of 7fff9h) is '0,' the frequency test bit (ft, d6 of 7fffch) is '1,' the alarm flag enable bit (afe, d7 of 7fff6h) is '0,' and the watchdog steering bit (wds, d7 of 7fff7h) is '1' or the watchdog register (7fff7h=0) is reset. note: a 4-second settling time must be allowed before reading the 512hz output. any deviation from 512hz indicates the degree and direction of oscillator frequency shift at the test temperature. for example, a reading of 512.010124hz would indicate a +20 ppm oscillator frequency error, requiring a 10 (wr001010) to be loaded into the calibration byte for correction. note that setting or changing the calibration byte does not affect the frequency test output fre- quency. the irq/ft pin is an open drain output which re- quires a pull-up resistor to v cc for proper opera- tion. a 500-10k w resistor is recommended in order to control the rise time. the ft bit is cleared on power-down.
m48t201y, m48t201v 24/32 battery low warning the m48t201y/v automatically performs battery voltage monitoring upon power-up and at factory- programmed time intervals of approximately 24 hours. the battery low (bl) bit, bit d4 of flags register 7fff0h, will be asserted if the battery voltage is found to be less than approximately 2.5v. the bl bit will remain asserted until comple- tion of battery replacement and subsequent bat- tery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. if a battery low is generated during a power-up se- quence, this indicates that the battery is below ap- proximately 2.5v and may not be able to maintain data integrity in the sram. data should be consid- ered suspect and verified as correct. a fresh bat- tery should be installed. if a battery low indication is generated during the 24-hour interval check, this indicates that the bat- tery is near end of life. however, data is not com- promised due to the fact that a nominal v cc is supplied. in order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. the snaphat ? top may be replaced while v cc is applied to the de- vice. note: this will cause the clock to lose time during the interval the battery/crystal is removed. the m48t201y/v only monitors the battery when a nominal v cc is applied to the device. thus appli- cations which require extensive durations in the battery back-up mode should be powered-up peri- odically (at least once every few months) in order for this technique to be beneficial. additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. initial power-on defaults upon application of power to the device, the fol- lowing register bits are set to a '0' state: wds; bmb0-bmb4; rb0-rb1; afe; abe; sqwe; w; r; ft (see table 14). table 14. default values note: 1. wds, bmb0-bmb4, rb0, rb1. 2. state of other control bits undefined. 3. state of other control bits remains unchanged. 4. assuming these bits set to '1' prior to power-down. conditi on w r ft afe abe sqwe watchdog register (1) initial power-up (battery attach for snaphat) (2) 000000 0 reset (3) 000000 0 power-down (4) 000111 0
25/32 m48t201y, m48t201v figure 13. crystal accuracy across temperature figure 14. calibration waveform ai00999 160 0 10203040506070 frequency (ppm) temperature c 80 10 20 30 40 100 120 140 40 60 80 20 0 20 d f = -0.038 (t - t 0 ) 2 10% f ppm c 2 t 0 =25 c ai00594b normal positive calibration negative calibration
m48t201y, m48t201v 26/32 v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, re- sulting in spikes on the v cc bus. these transients can be reduced if capacitors are used to store en- ergy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. a ceramic by- pass capacitor value of 0.1 m f (as shown in figure 15) is recommended in order to provide the need- ed filtering. in addition to transients that are caused by normal sram operation, power cycling can generate neg- ative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, stmicroelectronics recom- mends connecting a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount. figure 15. supply voltage protection ai00605 v cc 0.1 m f device v cc v ss
27/32 m48t201y, m48t201v part numbering table 15. ordering information example note: 1. the soic package (soh44) requires the battery package (snaphat ? ) which is ordered separately under the part number am4txx-br12sho in plastic tube or am4txx-br12shtro in tape & reel form. caution : do not place the snaphat battery package am4txx-br12sho in conductive foam as it will drain the lit hium button-cell battery. for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. table 16. snaphat ? battery table example: m48t 201y 70 mh 1 tr device type m48t supply and write protect voltage 201y = v cc = 4.5 to 5.5v; v pfd = 4.1v to 4.5v 201v = v cc = 3.0 to 3.6v; v pfd = 2.7v to 3.0v speed 70 = 70ns (for m48t201y) 85 = 85ns (for m48t201v) package mh (1) = soh44 temperature range 1=0to70 c 6=40to85 c shipping method for soic blank = tubes tr = tape & reel part number description package m4t28-br12sh lithium battery (48mah) snaphat sh m4t32-br12sh lithium battery (120mah) snaphat sh
m48t201y, m48t201v 28/32 package mechanical information figure 16. soh44 44-lead plastic small outline, snaphat, package outline note: drawing is not to scale. table 17. soh44 44-lead plastic small outline, snaphat, package mechanical data symb mm inches typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.46 0.014 0.018 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e 0.81 0.032 eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 a 0 8 0 8 n44 44 cp 0.10 0.004 soh-a e n d c l a1 a 1 h a cp be a2 eb
29/32 m48t201y, m48t201v figure 17. sh 4-pin snaphat housing for 48mah battery & crystal, package outline note: drawing is not to scale. table 18. sh 4-pin snaphat housing for 48mah battery & crystal, package mechanical data symb mm inches typ min max typ min max a 9.78 0.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shtk-a a1 a d e ea eb a2 b l a3
m48t201y, m48t201v 30/32 figure 18. sh 4-pin snaphat housing for 120mah battery & crystal, package outline note: drawing is not to scale. table 19. sh 4-pin snaphat housing for 120mah battery & crystal, package mechanical data symb mm inches typ min max typ min max a 10.54 0.415 a1 8.00 8.51 0.315 .0335 a2 7.24 8.00 0.285 0.315 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 17.27 18.03 0.680 .0710 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shtk-a a1 a d e ea eb a2 b l a3
31/32 m48t201y, m48t201v revision history table 20. document revision history date revision details november 1999 first issue 05/10/01 reformatted; added industrial temperature (table 2, 5, 7, 8, 9) 05/14/01 corrected table footnote (table 9) 05/30/01 change acontrollero references to asupervisoro 08/01/01 formatting changes from recent document review findings; e2 added to hookup (figure 4) 08/08/01 improve text in asetting the alarm clocko section 12/18/01 added ibat values for industrial temperature device (table 5) 05/13/02 modify reflow time and temperature footnote (table 2)
m48t201y, m48t201v 32/32 m48t201, m48t201y, m48t201v, 48t201, 48t201y, 48t201v, t201, t201y, t201v, sup erv isor, sup erv isor, supe rvi sor, sup erv isor, sup erv isor , su per v is or, supe rv isor , supe r- visor, su perv isor , su per vis or, sup erv isor , super vis or, su per vis or, su per visor, superv isor, timekeeper, timekee per , timekeeper, timekeeper, timek eeper , time- keeper , timekeeper, timekeeper, timek eeper , timekeeper , timekeepe r, timekeeper , timekeep er, timekeeper , timekeeper, timekeeper, timekeeper , timek eeper , timekeeper , timekeeper, timekeepe r, timekee per , timek eeper , timek eeper , timekeeper , nv ram , n vr am, nvr am, nvr am, nv ram , n vr am, n vra m, n vra m, nv ram, nvr am, n vram , nvr am, nv ram , nv ra m, nv ram , nv ram , n vra m, nv ram , nv ra m, nvra m, nvr am, n vram , nvr am, nv ram , nv ra m, nv ram , nvr am, n vra m, nvr am, nv ram, nvram , n vr am, n vram , nv ra m, nvra m, nvr am, nvr am, nv ram, nvra m, nvra m, nvra m, nv ram, nvr am, nv ram , nvr am, nvra m,nvr am, nv ram , n vram , nvram , rtc, rtc, rtc, rtc, rtc , rtc, r tc, r tc, r tc, r tc, rtc , rtc , rtc , rtc, r tc, rtc, r tc, rtc , r tc, rtc, rtc , rtc, r tc, rtc, r tc, rtc , r tc, rtc, rtc, rtc, rtc, r tc, rtc, r tc, rtc , r tc, rtc, rtc, rtc , rtc, rtc, rtc, r tc, rtc, r tc, rtc , rtc , r tc, r tc,r tc, rtc , rtc, rtc, r tc,r tc, rtc , rtc, r tc, rtc , rtc, rtc, rtc , rtc , r tc, rtc, microprocessor, microprocessor, micro processor, microprocessor, micro- process or, microprocess or, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocess or, microprocessor, microprocessor, microprocessor, microproces- sor, microprocessor, microprocessor, microprocessor, microprocess or, microprocessor, microprocessor, microprocessor, microprocess or, low , low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low , low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low , low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low , low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low , low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low , low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low , low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low , low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low , low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low , low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low , low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low , low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low , low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, ala rm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, a larm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, a larm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, a larm, alarm, alarm, alarm, alarm, alarm, watchdog, watch- dog, watchdog, watchdog, watchdog, watc hdog, watchdog, watchdog, watc hdog, watchdog, watc hdog, watchdog, watchdog, w atchdog, watchdog, w atchd og, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, w atchdog, watchdog, w atchdog, w atchdog, w atchdog, w atchdog, watc hdog, watc hdog, w atchdog, watchdog, w atchdog, w atchdog, watchdog, watchdog, watchdog, w atchdog, watchdog, watchdog, watchdog, watchdog, w atchdog, w atchdog, watchdog, watc hdog, watchdog, w atchdog, pfi, pfi, pfi, pfi, pfi , pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi,pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfi, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo , pfo, pfo, pfo, pfo, pfo, pfo, pfo, pfo, r eset, r eset, r eset, r eset, reset, reset, reset, reset, reset, reset, reset, r eset, reset, r eset, r eset, reset, r eset, r eset, reset, r eset, r es et, reset, reset, reset, reset, r eset, reset, r eset, r eset, reset, reset, r eset, reset, reset, r eset, reset, r eset, reset, reset, r eset, reset, reset, reset, reset, reset, reset, reset, reset, r eset, r eset, r eset, r eset, reset, r eset, r eset, r eset, r eset, r eset, reset, reset, r eset, reset, reset, r eset, reset, r eset, reset, reset, r eset, reset, reset, reset, reset, reset, reset, reset, reset, r eset, r eset, r eset, r eset, reset, r eset, r eset, r eset, r eset, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery , battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery , battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, sw itchover, sw itchover, switc hover, swi tchover, swi tchover, swi tchover, switchover, switc hover, sw itchover, swi tchover, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, comparator, compar ator, comparator, comparator, comparator, comparator, comparator, com- parator, comparator, c omparator, comparator, c omparator, c omparator, comparator, c omparator, c omparator, comparator, comparator, c omparato r, comparator, c omparator, c omparator, comparator, c omparator, c omparator, c omparator, comparator, c omparator, comparator, comparator, c omparator, comparator, c omparator, c omparator, compar ator, snap hat , sn aph at, sna pha t, sn aph at, snapha t, snap hat, sn aph at, sn aphat, sn aph at, sn aph at, sn aph at, sn aph at, sna pha t, snaph at, sna ph at, snapha t, snap hat, sn aph at, sn aph at, sn aph at , sn aph at, snapha t, sna pha t, snaph at, snap hat , sna phat , sna pha t, sna phat , sna ph at, sn aph at, sna pha t, sn aphat, sn aph at, sna pha t, sna ph at, soic , soic, soic, soic, soic, soic , soic, soic, soic, soic , soic , soic, soic , soic, soic, soic, soic, soic, soic, soic , soic, soic, soic, soic, soic, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v , 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 3.3v, 3.3v, 3.3v, 3.3v, 3.3v, 3.3v, 3.3v, 3.3v, 3.3v, 3.3v information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

▲Up To Search▲

Price & Availability of M48T201Y-70MH1

	To Download M48T201Y-70MH1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .